Programmable Frequency Divider Design for Multi – Ghz Phase Locked Loop (PLL) System

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output 16 to 1 multiplexer. To the extent of maximizing the frequency of operation, each frequency divider block has been realized using dynamic precharge-evaluation logic. The design of an improved dynamic logic DFF is presented. FPGA implementation of Frequency divider has been proposed in this project. This project involves two phases-simulation and synthesis of the VHDL codes using Modelsim SE 6. 1a and Xilinx Synthesis Technology (XST) of Xilinx ISE design suite 10. 1 tool. A VHDL specification can be executed in order to achieve high level satisfaction in its correctness before commencing design. Model sim is verification and simulation tool for VHDL, Verilog, System Verilog and it also supports mixed-signal language. It can simulate behavioral, RTL, and gate-level code separately or simultaneously. Model Sim also supports all ASIC and FPGA libraries, ensuring accurate timing simulations. Model Sim is known for delivering high performance, ease of use, and outstanding product support. The module for the Programmable frequency divider comprises basic digital components, such as frequency divide by 2, 3, 5, 7, 8, 13 and multiplexer. Keywords-Phase locked loop (PLL), Voltage controlled oscillator (vco), frequency synthesizer, FPGA, VHDL.